The course presents code optimisation for Intel Xeon Phi Knights Landing (KNL) architecture. This includes AVX512 vectorization, task-based and loop-based OpenMP parallelization, hybrid programming with OpenMP and MPI. Performance analysis tools will be discussed.
When: 30 Jan - 1 Feb 2018
Registration closes: 22 Jan 2018
Where: STFC Hartree Centre, Sci-Tech Daresbury, Cheshire, UK
Best for: Trainees who are able to work independently but would require guidance for solving complex problems
Prerequisites: Basic skills in C/C++/Fortran and OpenMP/MPI programming language; Basic skill in using a Linux HPC environment;
Learning Outcomes: On completion of this course, delegates will be able to understand the Intel Xeon Phi KNL architecture, the multiple memory and clustering models it has, and how to evaluate and optimise the performance of software on it.
Contact us: firstname.lastname@example.org
About Intel Xeon Phi:
The Intel Xeon Phi (codenamed Knight’s Landing) is a many-core CPU architecture; it has greater parallelism and a much larger number of cores than an ordinary central processing unit (CPU). In order to benefit from this architecture your code will have to execute concurrently across multiple cores and threads whilst exploiting the Single Instruction, Many Data (SIMD) paradigm. The Hartree Centre’s newest supercomputer, Scafell Pike, contains 800 Knight’s Landing nodes.