part of the Hartree Centre’s role as an Intel Parallel Computing Centre, a three-day
workshop took place on 23-25 May 2016 to help coders get to grips with Intel
Xeon Phi processors.
Intel Xeon Phi is sometimes referred to as an accelerator co-processor because
the architecture is different from ordinary CPUs (central processing units); it
has greater parallelism and much larger number of cores. This means that, in
order to make the most of it, programmers need to express more parallelism when
writing their code. Parallelism means executing a
code using multiple cores of the processor concurrently, each doing a different
task, in order to finish the overall execution faster.
Hartree Centre’s Sergi Siso, one of the course leaders, said: “These courses
are very interesting for us because we can interact directly with the users of
the new Intel Xeon Phi processors. At the same time, they learn from our
experiences using the technology over the last year, and how different HPC codes
can be made to run faster on these modern architectures. This time, Intel staff
also gave a presentation on an architecture that will only be released next
month, so people were very interested in this as they got a preview of the
Hartree Centre holds similar workshops annually so if you would like to get
involved in future events, or find out more about our role as an Intel Parallel
Computing Centre, please contact Sergi Siso.